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rf amp & servo signal processor s1l9226x 5 preliminary introduction as a pre-signal & servo signal processor for the disc-man, s1l9226x is a low voltage, low consumption current ic that can read cd-rw, and cd-r discs and can be applied to various products, such as the cdp/vcd/cd- mp3 for the disc-man. it is a hard-wired free-adjustment servo, which automatically controlled the control point of the pre-signal portion. features ? rf amplifier (cd, cd-r, cd-rw applicable) ? gain setting & monitoring for the cd-r, cd-rw disc ? rfamp offset adjustment ? focus error amp & febias adjustment ? tracking error amp & balance, gain adjustment ? fok, defect, mirror detect ? center voltage amplifier ? apc (automatic power control) ? rf agc & eq control (agc level control compatible) ? enhanced efm slice (double asymmetry method) ? focus servo loop & offset adjustment ? tracking servo loop & offset adjustment ? sled servo loop ? spindle servo loop ? auto-sequence ? fast search mode (1 - 36000 track jump) ? interruption countermeasure ? focus & tracking servo muting controlled by efm duty check ? rf peaking prevention system by efm duty check ? focus, tracking, spindle loop pole move option ? operating voltage 2.7v ? 3.3v ? power saving mode lpc control used by side beam signal, it related to pick-up assurance. when used pick-up, the specification is present extra. ordering information device package supply voltage operating temperature s1l9226x01 ? q0r0 48-lqfp-0707 2.7v ? 3.3v -20 c ? +75 c 48-lqfp-0707
s1l9226x rf amp & servo signal processor 4 preliminary block diagram 4 12 rf agc & eq control focus ok detect defect detect mirror gen center voltage apc. laser control & lpc tracking servo loop - gain & phase compensation - track jump - offset adjust - tzc gen. tracking error (rw) i/v amp rf & focus error (cd-rw) i/v amp hardware logic - auto-sequencer - fast search - febias, focus servo, tracking offset adj. - tracking balance & gain adjust - interruption detect - efm muting system sled servo & kick gen spindle servo lpf efm comparator micom data interface logic decoder focus servo loop - gain & phase compensation - focus search - offset adjust - fzc gen. eqo pd ld lpft teio tzc& sstop atsc teo tem slp slo slm feo fem spdlo spdlm eqi rfo rfm eqc vref pde pdf pdbd pdac istat mck mdata mlt reset wdck clvi lock asy efm 5 45 46 44 43 6 7 8 9 10 11 14 13 15 16 17 19 18 20 22 21 24 23 30 29 25 26 27 28 29 36 33 34 35 37 38 39 41 40 42 47 48 1 2 3 efmi dcci dcc0 mcp dcb vcc/ vdd frsh fset flb fgd fsi tgu
rf amp & servo signal processor s1l9226x 5 preliminary application diagram s1l9226x to micom from micom teo tem slp slo slm istat mck mdata mlt reset wdck clvi lock asy efm spm efmi vcc frsh fset flb fgd fsi tgu eqo eqi rfo rfm pd ld 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 pick-up ld pd a c b d f e vr vcc gnd 55k 55k 55k 55k 82k 82k 103 103 333 683 33 m f 2pf 22k 682 821 47 m f 430k 104 104 102 104 10k from micom from micom from micom 474 333 smef 8.2k 20k smds smdp 10k from dsp from dsp to dsp 474 103 10k 100k 88k 103 22k 683 47k 10 m f 120k 39k 104 100k 120k 391 222 from pick-up 150k 104 333 100k 104 47 m f 220 100 m f spo fem feo gnd tzc/sstop teio lpft atsc pdac pdf pdbd pde dcb mcp dcci dcco vref eqc 272 10k 1m w 104 2pf
s1l9226x rf amp & servo signal processor 4 preliminary pin configuration s1l9226x teo tem slp slo slm istat mck mdata mlt reset wdck clvi lock asy efm spm efmi vcc frsh fset flb fgd fsi tgu eqo eqi rfo rfm pd ld 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 spo fem feo gnd tzc/sstop teio lpft atsc pdac pdf pdbd pde dcb mcp dcci dcco vref eqc
rf amp & servo signal processor s1l9226x 5 preliminary pin description table 1. pin description pin no. symbol i/o description 1 rfm i rf summing amp. inverting input 2 rfo o rf summing amp. output 3 eqi i rfo dc eliminating input(use by mirror, fok ,agc & eq terminal) 4 eqo o rf equalizer output 5 efmi i efm slice input. (input impedance 47k) 6 vcc p main power supply 7 frsh i capcitor connection to focus search 8 fset i filter bias for focus,tracking,spindle 9 flb i capacitor connection to make focus loop rising band 10 fgd i terminal to change the hign frequency gain of focus loop 11 fsi i focus servo input 12 tgu i connect the component to change the high frequency of tracking loop 13 istat o internal status output 14 mck i micom clock 15 mdata i data input 16 mlt i data latch input 17 reset i reset input 18 clvi i input the spindle control output from dsp 19 wdck i 88.2khz input terminal from dsp 20 lock i sled run away inhibit pin (l: sled off & tracking gain up) 21 efm o efm output for rfo slice(to dsp) 22 asy i auto asymmetry control input 23 spm i spindle amp. inverting input 24 spo o spindle amp. output 25 slm i sled servo inverting input 26 slo o sled servo output 27 slp i sled servo noninverting input 28 tem i tracking servo amp.inverting input 29 teo o tracking servo amp. output 30 fem i focus servo amp. inverting input 31 feo o focus servo amp. output pin
s1l9226x rf amp & servo signal processor 4 preliminary maximum absolute ratings 32 gnd p main ground 33 tzc/ sstop i tracking zero crossing input & check the position of pick-up wherther inside or not 34 teio b tracking error output & tracking servo input 35 lpft i tracking error integration input (to automatic control) 36 atsc i anti-shock input 37 ld o apc amp. output 38 pd i apc amp. input 39 pdac i photo diode a & c rf i/v amp. inverting input 40 pdbd i photo diode b & d rf i/v amp. inverting input 41 pdf i photo diode f & tracking(f) i/v amp. inverting input 42 pde i photo diode e & tracking(e) i/v amp. inverting input 43 dcb i capacitor connection to limit the defect detection 44 mcp i capacitor connection to mirror hold 45 dcci o output pin to connect the component for defect detect 46 dcco i input pin to connect the component for defect detect 47 vref o (vcc+gnd)/2 voltage reference output 48 eqc i agc_equalize level control terminal & capacitor terminal to input in to vca item symbol rating unit power supply voltage v dd 2.7 ? 3.3 v absolute ratings v i 4.5 v operating temperature t opr -20 ? 75 c storage temperature t stg -40 ? 125 c table 1. pin description (continued) pin no. symbol i/o description
rf amp & servo signal processor s1l9226x 5 preliminary electrical characteristics table 2. electrical characteristics no. characteristics symbols test block spec unit min. typ. max. 1 supply current 2.7v iccty 5 10 20 ma 2 rf amp offset voltage vrfo rf amp -100 0 100 mv 3 rf amp offset voltage 2 vrfo2 -300 -200 -100 mv 4 rf amp oscillation voltage vrfosc 0 50 100 mv 5 rf amp voltage gain ac grf 15.5 18.5 23.5 db 6 rf thd characteristic rfthd - - 5 % 7 rf amp maximum output voltage vrfh 2.35 - - v 8 rf amp minimum output voltage vrfl - - 0.85 v 9 rf cdrw gain ac1 grwac1 1.05 1.30 1.55 - 10 rf cdrw gain ac2 grwac2 1.05 1.30 1.55 - 11 rf cdrw gain ac3 grwac3 1.05 1.30 1.55 - 12 focus error offset voltage vfeo1 focus error -525 -250 0 mv 13 focus error auto voltage vfeo2 -50 0 50 mv 14 istat state after febias control vistat1 2.2 - - v 15 focus positive offset 1 vfep1 0 40 80 mv 16 focus positive offset 2 vfep2 10 60 100 mv 17 focus positive offset 3 vfep3 50 120 180 mv 18 focus negative offset 1 vfen1 -80 -40 0 mv 19 focus negative offset 2 vfen2 -100 -60 -10 mv 20 focus negative offset 3 vfen3 -180 -120 -50 mv 21 focus error voltage gain 1 gfeac 19 23 27 db 22 focus error voltage gain 2 gfebd 19 23 27 db 23 focus error voltage gain difference d gfe -3 0 3 db 24 focus error rw down gferwd 0.4 0.7 1.0 - 25 focus error ac difference vfeacp 0 50 100 mv 26 ferr maximum output voltage h vfepph 2.3 - - v 27 ferr minimum output voltage l vfeppl - - 0.4 v 28 agc max gain gagc agc_eq 15 19 22 db 29 agc eq gain geq -3 1 2.5 db 30 agc normal gain gagc2 3 6 9 db 31 agc compress ratio cagc 0 2.5 5 db
s1l9226x rf amp & servo signal processor 4 preliminary table 2. electrical characteristics (continued) no. characteristics symbols test block spec unit min. typ. max. 32 agc frequency fagc agc_eq -5.0 0 2.5 db 33 agc level control agcl 0.95 1.125 1.25 - 34 agc rf sel agcs 15.5 19.5 23.5 db 35 terr gain voltage gain 1 gtef1 tracking error 4.5 7.5 10.5 db 36 terr gain voltage gain 2 gtef2 0.98 2.25 4.5 - 37 terr gain voltage gain 3 gtef3 0.98 1.3 1.6 - 38 terr gain voltage gain 4 gtef4 0.95 1.15 1.30 - 39 terr gain voltage gain 5 gtef5 0.90 1.075 1.15 - 40 terr gain voltage gain 6 gtef6 0.98 1.15 1.30 - 41 terr gain voltage gain 7 gtef7 0.98 1.35 1.70 - 42 terr balance gain gtee 10.5 13.5 16.5 db 43 terr balance mode 1 tbe1 0.95 1.05 1.12 - 44 terr balance mode 2 tbe2 0.95 1.05 1.12 - 45 terr balance mode 3 tbe3 0.95 1.05 1.12 - 46 terr balance mode 4 tbe4 1.0 1.25 1.5 - 47 terr balance mode 5 tbe5 1.0 1.20 1.4 - 48 terr balance mode 6 tbe6 1.0 1.3 1.75 - 49 terr maximum output voltage h vtpph 1.9 - - v 50 terr minimum output voltage l vtppl - - 0.8 v 51 terr rw f gain 1 grwtf1 1.05 1.75 2.50 - 52 terr rw f gain 2 grwtf2 1.05 1.35 1.80 - 53 terr rw f gain 3 grwtf3 1.00 1.30 1.65 - 54 terr rw e gain 1 grwte1 1.05 1.35 1.65 - 55 terr rw e gain 2 grwte2 1.05 1.35 2.00 - 56 terr rw e gain 3 grwte3 1.00 1.30 1.65 - 57 apc psub voltage l apsl apc - - 1.0 v 58 apc psub voltage h apsh & 1.8 - - v 59 apc psub ldoff apslof laser 2.4 - - v 60 apc current drive h acdh control 1.35 - - v 61 apc current drive l acdl - - 1.35 v 62 mirror minimum operating frequency fmirb mirror - 550 900 hz 63 mirror maximum operating frequency fmirp 30 75 - khz
rf amp & servo signal processor s1l9226x 5 preliminary table 2. electrical characteristics (continued) no. characteristics symbols test block spec unit min. typ. max. 64 mirror am characteristic fmira mirror - 400 600 hz 65 mirror minimum input voltage vmirl - 0.1 0.2 v 66 mirror gain option 1 mirro1 10 - - khz 67 fok threshold voltage vfokt fok -450 -360 -300 mv 68 fok threshold voltage 2 vfokt2 -450 -560 -220 mv 69 fok output voltage h vfohh 2.2 - - v 70 fok output voltage l vfokl - - 0.5 v 71 fok feeq. characteristic ffok 40 45 50 khz 72 defect bottom voltage fdfctb defect - 670 1000 hz 73 defect cutoff voltage fdfctc 2.0 4.7 - khz 74 defect minimum input voltage vdfctl - 0.3 0.5 v 75 defect maximum input voltage vdfcth 1.8 - - v 76 defect option gain fdfctg - 670 1000 hz 77 normal efm duty voltage 1 ndefmn efm slice -50 0 50 mv 78 normal efm duty symmetry ndefma 45 50 55 % 79 normal efm duty voltage 3 ndefmh 0 50 100 mv 80 normal efm duty voltage 4 ndefml -100 -50 0 mv 81 normal efm minimum input voltage ndefmv - - 0.12 v 82 normal efm duty difference 1 ndefm1 20 50 80 mv 83 normal efm duty difference 2 ndefm2 20 50 80 mv 84 efm2 duty voltage 1 edefmn1 enhanced -50 0 50 mv 85 efm2 duty symmetry edefma efm slicer 45 50 55 % 86 double asy voltage 1 defm1 -375 -250 -125 mv 87 double asy voltage 2 defm2 125 250 375 mv 88 efm2 minimum input voltage edefmv - - 0.12 v 89 fzc threshold voltage vfzc interface 30 69 105 mv 90 anti-shock detection h vatsch 20 60 100 mv 91 anti-shock detection l vatscl -100 -60 -20 mv 92 tzc threshold voltage vtzc -150 0 150 mv 93 sstop threshold voltage vsstop -155 -90 -5 mv 94 tracking gain win t1 vtgwt1 190 250 310 mv 95 tracking gain win t2 vtgwt2 90 150 210 mv
s1l9226x rf amp & servo signal processor 4 preliminary table 2. electrical characteristics (continued) no. characteristics symbols test block spec unit min. typ. max. 96 tracking gain win t3 vtgwt3 interface 240 300 360 mv 97 tracking gain win t4 vtgwt4 140 200 260 mv 98 tracking gain win t5 vtgwt5 440 500 560 mv 99 tracking gain win t6 vtgwt6 340 400 460 mv 100 tracking bal win t1 vtbwt1 -50 0 50 mv 101 tracking bal win t2 vtbwt2 -50 0 50 mv 102 reference voltage vref vref -100 0 100 mv 103 reference current h irefh -100 0 100 mv 104 reference current l irefl -100 0 100 mv 105 f. servo off offset vosf1 focus servo -100 0 100 mv 106 f. servo dac on offset vosf2 0 250 550 mv 107 f. servo auto offset vaof -65 0 65 mv 108 f. servo auto istat vistat2 2.2 - - v 109 ferr febias status vfebias -50 0 50 mv 110 f. servo loop gain gf 17 21.5 24 db 111 f. servo output voltage h vfoh 2.2 - - v 112 f. servo output voltage l vfol - - 0.5 v 113 f. servo oscillation voltage vfosc 0 100 200 mv 114 f. servo feed through gff - - -35 db 115 f. servo search voltage h vfsh 0.30 0.50 0.70 v 116 f. servo search voltage l vfsl -0.70 -0.50 -0.30 v 117 focus full gain gfsfg 40.0 44.5 49.0 db 118 f. servo ac gain 1 gfa1 17.0 21.0 25.0 db 119 f. servo ac phase 1 pfa1 30 60 90 deg 120 f. servo ac gain 2 gfa2 14.0 17.5 21.0 db 121 f. servo ac phase 2 pfa2 30 60 90 deg 122 f. servo muting gmutt - - -15 db 123 f.servo ac gain difference gfad 1.5 5 8 db 124 f. servo ac characteristic 1 gfac1 1.75 2.25 2.80 125 f. servo ac characteristic 2 gfac2 1.05 1.55 2.05 - 126 f. servo ac characteristic 3 gfac3 1.05 1.55 2.05 -
rf amp & servo signal processor s1l9226x 5 preliminary table 2. electrical characteristics (continued) no. characteristics symbols test block spec unit min. typ. max. 127 t. servo dc gain gto tracking 13.0 15.5 18.0 db 128 t. servo off offset vost1 servo -100 0 100 mv 129 t. servo dac offset vtdac 150 320 700 mv 130 t. servo auto offset vtaof -55 0 70 mv 131 t.servo stat status vtstat 2.2 - - v 132 t. servo oscillation vtosc 0 100 185 mv 133 t. servo atsc gain gatsc 17.5 20.5 23.5 db 134 t. servo lock gain glock 17.5 20.5 23.5 db 135 t. servo gain up gtup 17.5 20.5 23.5 db 136 t. servo output voltage h vtsh 2.2 - - v 137 t. servo output voltage l vtsl - - 0.5 v 138 t. servo jump h vtjh 0.30 0.5 0.70 v 139 t. servo jump l vtjl -0.70 -0.5 -0.30 v 140 t. servo dirc h vdirch 0.30 0.5 0.70 v 141 t. servo dirc l vdircl -0.70 -0.5 -0.30 v 142 t. servo output voltage l gtff - - -39 db 143 t. servo ac gain 1 gta1 10.5 14.5 17.5 db 144 t. servo ac phase 1 pta1 -180 -135 -90 deg 145 t. servo ac gain 1 gta2 18.1 23.1 26.1 db 146 t. servo ac phase 1 pta2 -180 -135 -90 deg 147 t. servo full gain gtfg 32 36 40 db 148 t. servo ac characteristic1 gtac1 1.50 2.00 2.50 - 149 t. servo ac characteristic2 gtac2 0.40 0.80 1.30 - 150 t. servo loop mutt ac tsmtac 0 50 100 mv 151 sl. servo dc gain gsl sled servo 11.0 14.0 17.0 db 152 sl. servo feed through gslf - - -34 db 153 sled forward kick vskh 0.40 0.60 0.80 v 154 sled reverse kick vskl -0.80 -0.60 -0.40 v 155 sled output voltage h vslh 2.2 - - v 156 sled output voltage l vsll - - 0.5 v 157 sled lock off vslock -100 0 100 mv
s1l9226x rf amp & servo signal processor 4 preliminary table 2. electrical characteristics (continued) no. characteristics symbols test block spec unit min. typ. max. 158 sp. servo 1x gain gsp clv servo 13.5 16.5 19.5 db 159 sp. servo 2x gain gsp2 19.0 23.0 27.0 db 160 sp. servo output voltage h vsph 2.2 - - v 161 sp. servo output voltage l vspl - - 0.5 v 162 sp. servo ac gain 1 gspa1 -3.0 5.0 12.0 db 163 sp. servo ac phase 1 pspa1 -120 -90 -50 deg 164 sp. servo ac gain 2 gspa2 3.0 10.0 17.0 db 165 sp. servo ac phase 2 pspa2 -120 -80 -50 deg 166 sp.servo ac gain 3 gsp3 0.85 3 5.0 -
rf amp & servo signal processor s1l9226x 5 preliminary operation description micom command $0x, $1x tracking gain setting according to anti-shock item address data istat output d7 d6 d5 d4 d3 d2 d1 d0 focus control 0 0 0 0 fs4 focus on fs3 gain down fs2 search on fs1 search up fzc tracking control 0 0 0 1 anti - shock brake - on tg2 gain set tg1 gain set atsc d7 d6 d5 d4 d3 d2 d1 d0 istat anti - shock lens. brake - on tg2 (d3 = 1) tg1 atsc 0 1 0 1 0 1 0 1 0 0 0 1 anti - shock off anti - shock on lens brake off lens brake on high - freq. gain down high - freq. gain normal gain normal gain up item hex as = 0 as = 1 tracking gain control tg2 tg1 tg2 tg1 tg1. tg2 = 1 ? gain up $10 0 0 0 0 $11 0 1 0 1 $12 1 0 1 0 $13 1 1 1 1 $14 0 0 0 0 $15 0 1 0 1 $16 1 0 1 0 $17 1 1 1 1 $13, $17, $1b, $1f (as0) $18 0 0 1 1 $13, $17, $18, $1c (as1) $19 0 1 1 0 mirror muting turns off when the tracking $1a 1 0 0 1 gain goes up $1b 1 1 0 0 $1c 0 0 1 1 $1d 0 1 1 0 $1e 1 0 0 1 $1f 1 1 0 0
s1l9226x rf amp & servo signal processor 4 preliminary $2x d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 tracking servo mode sled servo mode operation of mode (tm1-tm7) mode tm7 tm5 tm4 tm3 tm2 tm1 tm1 $20 1 0 1 0 1 1 0 0 track. servo off $21 1 0 1 0 1 0 0 1 track. servo on $22 1 0 0 0 1 1 0 tm2 $23 1 1 1 0 1 1 0 0 sled. servo on $24 1 0 1 0 1 1 1 1 sled. servo off $25 1 0 1 0 1 0 1 tm4 tm3 track. kick $26 1 0 0 0 1 1 1 0 0 fwd. jump $27 1 1 1 0 1 1 1 0 1 jump off $28 1 0 1 0 0 1 0 1 1 rev. jump $29 1 0 1 0 0 0 0 tm6 tm5 sled kick $2a 1 0 0 0 0 1 0 0 0 fwd kick $2b 1 1 1 0 0 1 0 0 1 kick off $2c 1 0 1 1 1 1 0 1 1 rev kick $2d 1 0 1 1 1 0 0 tm7 (jump) $2e 1 0 0 1 1 1 0 1 lens brake on $2f 1 0 0 1 1 1 0
rf amp & servo signal processor s1l9226x 5 preliminary dirc (direct 1 track jump) tracking condition register $3x item hex dirc = 1 dirc = 0 dirc = 1 tm 654321 654321 654321 tracking mode $20 000000 001000 000011 $21 000010 001010 000011 $22 010000 011000 100001 $23 100000 101000 100001 $24 000001 000100 000011 $25 000011 000110 000011 $26 010001 010100 100001 $27 100001 100100 100001 $28 000100 001000 000011 $29 000110 001010 000011 $2a 010100 011000 100001 $2b 100100 101000 100001 $2c 001000 000100 000011 $2d 001010 000100 000011 $2e 011000 000100 100001 $2f 101000 100100 100001 address focus & sled focus search sled kick t.servo cpeak mutting tracking jump d15-d12 d11 d10 d9 d8 d7 d6 d5 d4 0011 level value ps4 search+2 ps3 serach+1 ps2 kick+2 ps2 kick+1 mutting when above efm11t ps5 jump +1 ps6 jump 1/2 ps7 jump 1/4 1x 0 0 0 0 0: off 1: on 0 0 0 0x (0u) 0 0 1 0.25x (1.25u) 2x 0 1 0 1 0 1 0 0.50x (2.50u) 0 1 1 0.75x (3.75u) 3x 1 0 1 0 1 0 0 1.00x (5.00u) 1 0 1 1.25x (6.25u) 4x 1 1 1 1 1 1 0 1.50x (7.50u) 1 1 1 1.75x (8.75u) initial 0 0 0 0 0 1 0 0
s1l9226x rf amp & servo signal processor 4 preliminary select (first 8 bits of 16 bits) address intc fset (focus, tracking cvl pole freq. setting resistor) d15-d12 d3 d2 d1 d0 0011 f.servo cpeak mutt fsetc fset2 24k fset1 12k mutting when above efm11t 0 x x external resistor applied 1 (104k) 0 0 140k (580k) 0 1 116k (480k) 1 0 128k (530k) 1 1 104k (430k) initial 0 1 1 1 d15 d14 d13 d12 d11 d10 d9 d8 istat 0 0 1 1 focus servo search level control sled servo kick level control sstop ps4 ps3 ps2 ps1 search +2 search +1 kick +2 kick +1 data mode (level) search x1 $30xx-$33xx kick x1 $30xx, $34xx, $38xx, $3cxx search x2 $34xx-$37xx kick x2 $31xx, $35xx, $39xx, $3dxx search x3 $38xx-$3bxx kick x3 $32xx, $36xx, $3axx, $3exx search x4 $3cxx-$3fxx kick x4 $33xx, $37xx, $3bxx, $3fxx data s.x1, k.x1 s.x2, k.x2 s.x3, k.x3 s.x4, k.x4 $30xx $35xx $3axx $3fxx
rf amp & servo signal processor s1l9226x 5 preliminary auto-sequence mode speed related command ($f00, f03) address data 0 1 0 0 d3 d2 d1 d0 auto-sequence cancel 0 0 0 0 auto-focus 0 1 1 1 1-track jump 1 0 0 0: fwd 10-track jump 1 0 1 1: rev 2n-track jump 1 1 0 m-track jump 1 1 1 fast search 0 1 0 address data d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 0 0 0 1x speed ($f00, $f04, $08, $f0c) x x 0 0 2x speed ($f03, $f07, $f0b, $f0f) x x 1 1
s1l9226x rf amp & servo signal processor 4 preliminary ram register set item data address d7 d6 d5 d4 d3 d2 d1 d0 blind a, e overflow. c $50xx 0.18ms 0.09ms 0.04ms 0.02ms brake. b 0.36ms 0.18ms 0.09ms 0.04ms fast f 23.2ms 11.6ms 5.80ms 2.90ms fast k 0.72ms 0.36ms 0.18ms 0.09ms ini. 1 0 0 0 1 0 0 0 control $51xx ps3x pstzc ats fzcoff trsts tzcic mcc1 eqr register sstop on/off tzc on/off atsc on/off fzc on/off t.bal & gainreset tzc. input eqc output agc in level 0 off off(sstop) t.bal off reset terr rfo 2/3 in 1 on on (tzc) atsc on set ferr eqo normal ini. 1 1 1 1 1 0 1 1 control $52xx fjts peakc feb5 feb4 feb3 feb2 feb1 feb0 register teo output when fast search efm peaking ref posi-offset(3v) ref voltage 3v depend on voltage febias offset fsio offset control the option rfo nega-offset fixed unrelated voltage msb 10mv/step lsb msb 10mv/step lsb 0 t.jump off 00 0mv off on (-150mv) 00 -250mv 01 +125mv 01 0mv 1 t-off (teo off) on 10 0mv on (+150mv) off 10 -125mv 11 +250mv 11 0mv ini. 1 0 0 0 0 1 1 1 febias offset regard on control before control the febias offset $51xx tzcic is set as the ferr ?1? and monitored tzc output . the istat output set + offset , febias offset control in sequence. if istat of tzc output set - offset, $52xx is set as the feb2 ?0?. after get - offset, febias offset control in sequence. * remark : phase of tzc output is opposite the input.
rf amp & servo signal processor s1l9226x 5 preliminary address hex d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 kick d $6xxx 11.6ms 5.80ms 2.90ms 1.45ms fast r 23.2ms 11.6ms 5.80ms 2.90ms pwm duty pd 8 4 2 1 pwm width pw 11.0ms 5.43ms 2.71ms 1.35ms ini. 0 1 1 1 1 0 1 0 0 0 1 0 2n tra. n m tra. m $7xxx 4096 2048 1024 512 256 128 64 32 16 8 4 2 fast searcht $7xxx 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 ini. 0 0 0 0 0 0 1 1 1 1 1 1 brake point p $cxxx 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 ini. 0 0 0 0 0 0 1 1 1 0 0 0 clv on/off register clv on, efm on $99x1~$99xf x x x x x x x 1 clv off, efm off $99x0 x x x x 0 0 0 0 ini 1 0 0 1 x x x x 0 0 0 0 notice. the actual value may be slightly different from the set value. a set value + 4 - 5 wdck b, d, e set value + 3 wdck c set value + 5 wdck n, m, t, p set value + 3 trcnt caution - among the 16 settings of pwm width 'pw' only one from d3, d2, d1, and d0 can be selected. (not 4bit combination) - more than 512 tracks are not recommended when 2n track and m track are used. (algorithm possesses problem generation) - because pwm duty 'pd' can have 1 - 2 errors, should be set to "set value + 2"
s1l9226x rf amp & servo signal processor 4 preliminary automatic control command tracking balance and gain control tracking balance and gain control window & apc on/off address address data d7 d6 d5 d4 d3 d2 d1 d0 tracking bal. $800x - $801x 0 0 0 b4 b3 b2 b1 b0 initial v. 0 1 1 1 1 tracking gain. $810x - $811x 0 0 0 g4 g3 g2 g1 g0 initial v. 1 0 0 0 0 address data d7 d6 d5 d4 d3 stgw stbw f.s.o.c f.e.o.c ldon $84x tracking gain control windows tracking balance control windows f.servo offset control fb.bias offset control $85 ld on/off tgl tgh istat 250mv 200mv -20mv-20mv off off off 150mv 300mv -30mv-30mv on on on initial 0 0 0 0 0
rf amp & servo signal processor s1l9226x 5 preliminary additional register set $8exx focus & tracking servo filter control command d3 d2 d1 d0 d3 d2 d1 d0 rsts eqoc dfct1 dfct2 dirc rstf agcl eqb $86x focus servo offset dac reset eq0 offset vref(1) vcc follow(0) defect input gain input offset addition &87x direct 1 track jump focus error dac reset eq0 output level up eq respose gm 0 reset normal 1.5x vr+0.25v 0 on reset up 12u 1 set buffer 1x vr+0.35v 1 off set normal 18u initial 1 1 1 1 initial 1 1 1 1 address data d7 d6 d5 d4 d3 d2 d1 d0 $8exx clv freq. movement 0: low frequency 1: high frequency t. servo phase shift 0: low frequency 1: high frequency fcous freq. movement 0: low frequency 1: high frequency 0 on on on on on on on on 1 off off off off off off off off initial v. 1 0 1 1 0 1 1 0
s1l9226x rf amp & servo signal processor 4 preliminary $8fxx tracking servo offset control command address data d7 d6 d5 d4 d3 d2 d1 d0 $8f00 ? $8f1f x x x tracking servo offset control command 8f(000xxxxx) $8f1f ? $8f00 (-160mv ? +160mv) control window is used with the balance window and monitors the istat output because tracking offset of approximately +30mv - +50mv is ideal in the system, consider the control setting by raising to ($8f1f ? $8f00) 3 - 5 steps after controlling the offset to 0mv. consider the measure setting by $8010 command of tracking switch and $811f command of tracking gain switch after $24 command. initial v. 0 0 0 1 0 0 0 0
rf amp & servo signal processor s1l9226x 5 preliminary photo-diode i/v amp gain setting for cd-r and cd-rw address data d7 d6 d5 d4 rf & ferr gain rfo only gain rfo total focus gain down rwc3 1.5x rw2c 2.0x rwc1 1.25x i/v amp equivalence resistance input resistance 55k gain summing resistance rfo feed resistance ratio 22k rfo loop total $82xx rfo focus error rfo only 1 stage gain 2 stage gain rfo total compare to f 07(0f) focus gain down bit 1 1 1 58.5k 1.06 10k 22k/10k=2.2 9.33 1.00 06(0e) 1 1 0 91.5k 1.66 10k 22k/10k=2.2 14.61 1.56 05(0d) 1 0 1 121.75k 2.21 10k 22k/10k=2.2 19.45 2.08 04(0c) 1 0 0 154.75k 2.81 10k 22k/10k=2.2 24.73 2.65 03(0b) 0 1 1 154.75k 2.81 10k 22k/10k=2.2 24.73 2.65 02(0a) 0 1 0 187.75k 3.41 10k 22k/10k=2.2 30.00 3.21 01(09) 0 0 1 218.00k 3.96 10k 22k/10k=2.2 34.84 3.73 00(08) 0 0 0 251.00k 4.56 10k 22k/10k=2.2 40.33 4.32 0 down up up up set the 8 when cd-rw mode 1 normal normal normal normal initial 1 1 1 1
s1l9226x rf amp & servo signal processor 4 preliminary tracking error cd-rw mode gain address data d3 d2 d1 d0 tracking error terr total speak rwc8 1.5x rwc7 2.0x rwc6 1.5x i/v amp equivalence resistance input resistance 82k gain resistance difference tracking feed resistance ratio 22k terr loop total $82xx tracking error gain te difference 1 stage gain 2 stage gain terr total compare to 7 07(0f) efm duty check freq. 1 1 1 391k 1.06 30k 96k/30k=32 3.392 1.00 06(0e) 1 1 0 583k 1.66 30k 96k/30k=32 5.312 1.56 05(0d) 1 0 1 786k 2.21 30k 96k/30k=32 7.07 2.08 04(0c) 1 0 0 979k 2.81 30k 96k/30k=32 8.992 2.65 03(0b) 0 1 1 979k 2.81 30k 96k/30k=32 8.992 2.65 02(0a) 0 1 0 1171k 3.41 30k 96k/30k=32 10.91 3.21 01(09) 0 0 1 1374k 3.96 30k 96k/30k=32 12.67 3.73 00(08) 0 0 0 1567k 4.56 30k 96k/30k=32 14.592 4.32 0 88k up up up set the 0 (4.01x) when cd-rw mode setting (because need long lead in time to check 8 setp) 1 44k norma l norma l normal initial 0 1 1 1
rf amp & servo signal processor s1l9226x 5 preliminary istat output monitor select mode & rfo offset control. address data d7 d6 d5 d4 d3 d2 d1 d0 mga1 mga2 rfoc tocd emodec cstat rfbc gsel $83xx mirror input gain mirror bias addition t.gain win input select tracking offset comtrol on/off efm slice mode istat output option rfo offset fok select t.gain windows sel 0 2x off focus error off double asy cstat fok 200/300mv 1 1.5x on t.gain on vref cstatb rfo offset 400/500mv initial 1 0 1 1 1 1 0 0 command. solution cd-rw detect method focus error cd-rw distinction the monitor output in the table above is set as the focus error output and the focus error output level comparison $81xx is sent to istat1 and istat2 to allow the micom to monitor the focus error output. after $81xx is sent, it possible to monitor because the tracking gain window comparator are used commonly. with search command ($47), if the intensity of radiation set its target, focus search level is 1vp-p, and peak value is 0.5v. as the table below, windows level transmit $84cx $513x command, istat1 monitored at 500mv gsel istat output mode tgl gsel(tgh) 0 1 $844x 250mv 200mv 400mv use the 6 types tracking gain window to distinguish the cd and cd- rw disc. $84cx 150mv 300mv 500mv istat cstat 5x 6x 7x 1x istat output 1 cpeak fzcb tzcb atsc change the istat output by cstat 0 fsdfct mirror dfcint fok, lock or output change the istat output by cstat initial. 1 1 1 1 change the istat output by cstat 0x fok 2x trcnt 3x sstop 4x auto seq busy signal $841 focus error offset window $842 focus servo offset window $cxxxx tracking gain window (tgl) $80xx tracking balance window $81xx tracking gain window (tgh) $8fxx tracking servo offset window $99xx $9900 clv off $9901 - $991f clv on clv command decording
s1l9226x rf amp & servo signal processor 4 preliminary auto-sequence this function executes the chain of commands that execute auto-focus, track jump, and move. mlt latches the data at time l, and istat is l during auto-sequence. it output h upon. auto focus flow-chart timing chart auto-focus receives the auto-focus command from the micom in the focus search down state and focus search up. the ssp becomes focus servo on when fzc changes to l after the internal fok rzc satisfy 'h', all the time set blind 'e' (register $5x). all the internal auto focus executes ended. and this status is sent to micom through the istat output. focus search up focus servo on no yes no yes no yes auto focus end fok = h fzc = h fzc = l during blind "e" time set by register 5, fok and fzc executions repeat until they become "h". $47 latch blind time e fok, fzc -> h search up search down $02 $03 $03 $03 $08 internal status focus output fok mlt focus servo on fzc istat
rf amp & servo signal processor s1l9226x 5 preliminary 1 track jump {$48(fwd), $49(rev)} flow-chart 1 track jump timing chart {$48(fwd), $49(rev) inside ( ) reverse} receives $48 ($49) for 1 track jump and sets the blind and brake times through register $5x. track jump sled servo off wait brake "b" no yes wait (blind a) track rev jump track, sled servo on 1 track jump end trcnt = forward jump when $48 and reverse jump when $49 wait using the wdck reference clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) repeat check of whether trcnt is continuously in "h" state with the wdck reference clock for the brake "b" time, set by register 5, at the trcnt rising edge. $47 ( $49) blind time a wait blind time b trcnt "h" tracking farward jump track servo on tracking revrese jump track servo on sled servo on sled servo off sled servo on $25 $28 ($2c) $28 ($2c) $2c ($28) $25 istat sled output track output trcnt mlt internal status
s1l9226x rf amp & servo signal processor 4 preliminary 10 track jump {$4a(fwd), $4b(rev)} flow-chart 10 track jump timing chart {$4a(fwd), $4b(rev) inside ( )reverse } 10 track jump executes the tracking forward jump up to trcnt 5track count and turns on the tracking and sled servos after a tracking reverse jump until trcnt 1's cycle is longer than the overflow 'c' time. this operation checks whether the actuator speed is sufficient to turn on the servo. track fwd jump sled fwd kick trcnt = 5 no yes wait (blind a) track rev jump, sled fwd kick track, sled servo on no yes 10 track jump end c = over flow? foward jump & kick when $4a and reverse jump & kick when $4b. wait using the wdck reference clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) tracking reverse jump & sled forward kick when $4a and tracking forward jump & reverse kick when &4b. repeat check of trcnt 1's cycle with the wdck reference clock to determine if the cycle is long than the overflow "c" time, set by register 5. $4a ( $4b) blind time a wait trcnt 5 count tracking forward jump track servo on tracking revrese jump track servo on sled servo on sled forward kick sled servo on $25 $2a ($2f) $2a ($2f) $2e ($2b) $25 istat sled output track output trcnt mlt over flow time c trcnt 1's time check fwd rev internal status
rf amp & servo signal processor s1l9226x 5 preliminary 2n track jump flow-chart track fwd jump, sled fwd kick no yes wait (blind a) track rev jump, sled fwd kick wait (kick "d") no yes track servo on, sled fwd kick tracking & sled servo on 2n track jump end trcnt = n? c = over flow? foward jump & kick when $4c and reverse jump & kick when $4d. wait using the wdck reference clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) tracking reverse jump & sled forward kick when $4c and tracking forward jump & reverse kick when $4d. repeat check of trcnt 1's cycle with the wdck reference clock to determine if the cycle is longer than the overflow "c" time, set by register 5. when $4c, the sled forward kick continues for kick "d" time. when $4d, the sled reverse kick continues for kick "d" time.
s1l9226x rf amp & servo signal processor 4 preliminary 2n track jump timing chart {$4c(fwd), $4d(rev) inside ( ) reverse } similar to 10 tracks and executes by adding sled kick by the amount of kick 'd' time and the servo turns on after lens brake starts. $4c ( $4d) blind time a wait trcnt n count tracking forward jump track servo on tracking revrese jump track servo on sled servo on sled forward kick sled servo on $25+$17 $2a ($2f) $2a ($2b) $2e ($2b) $25+$18 istat sled output track output trcnt mlt over flow time c trcnt 1's cycle time check fwd rev c c kick time d sled fwd kick for d time q data read enable $26($27) internal status
rf amp & servo signal processor s1l9226x 5 preliminary m track jump {$4e(fwd), $4f(rev)} flow-chart m track jump timing chart {$4e(fwd), $4f(rev) inside () reverse} makes trcnt to clock and counts to the value of m count, set by register 7, to execute sled kick. track servo off, sled fwd kick no yes wait (blind a) tracking & sled servo on m track jump end trcnt = m? sled fwd kick when $4e and rev kick when $4f. wait using the wdck reference clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) count trcnt with the clock for m amount, set by register 7. $4e ( $4f) blind time a wait trcnt n count tracking servo off track servo on treck servo on sled servo on sled forward kick sled servo on $25 $22 ($23) $22 ($23) $22 ($23) $25 istat sled output track output trcnt mlt fwd rev internal status
s1l9226x rf amp & servo signal processor 4 preliminary fast search flow-chart track servo on, sled fwd kick wait (blind f) no yes track fwd jump, sled fwd kick wait (blind k) track fwd jump, sled fwd pwm kick no yes track servo on, sled rev kick wait (rev. kick "r") tracking & sled servo on fast search end trcnt = t? trcnt = p? sled forward kick when $44 and sled reverse kick when $45. tracking forward kick jump and sled forward kick when $44 and tracking reverse jump and sled reverse kick when $45 execute the above conditions until trcnt is the same as the brake point "p" count value, set by register 7. repeat checks trcnt, until trcnt equals t set by register 7, like the pd and pw set by register 6, pwms duty is decided with the pws pwm1 period width used as the period, and pds high. low duty used as standard 4 bits (number selected from 0 - 15) when $44, the sled forward kick continues for kick "r" time. when $45, the sled reverse kick continues for kick "r" time.
rf amp & servo signal processor s1l9226x 5 preliminary fast search timing chart {$44(fwd), $45(rev) inside () reverse} to note during use of auto-sequence 1. must send tracking gain up and brake on ($17) during 1, 10, 2n, track jump, and fast search. 2. before the auto-sequence mode, mlt becomes 'l' and sequence operation executes at the initial wdck falling edge after data latch. 3. during play, determine as fok and gfs, not istat. 4. tracking gain up, brake, anti-shock and focus gain down are not executed in auto-sequence, and separate command must be provided. 5. if the auto-sequence does not operate as istat max time over, apply $40 and use after clearing the ssp internal state. 6. the above indicated wdck receives 88.2khz from dsp. (2x ? 176khz) 7. the auto-sequence internal trcnt and the actual trcnt are slightly different. 8. problems can be generated in the algorithm for 2n and m tracks if jump of more than 512 tracks are attempted; therefore, use them for less than 512 track jumps, if at all possible. 9. use the fast-search algorithm for more than 512 tracks, if possible. $44 ( $45) blind time f wait trcnt p count sled servo on tracking forward jump track servo on $25+$17 $26 ($27) $2a ($2f) $26 ($27) $25+$18 istat sled output track output trcnt mlt fwd rev blind k wait trcnt t count kick "r" walt sled rev kick sled servo on sled servo on sled forward kick $5xx1 tracking servo mutt sled servo kick internal status
s1l9226x rf amp & servo signal processor 4 preliminary tracking balance control concept in tracking balance control, the micom compares and monitors the previously set dc voltage window and the tracking error dc offset, extracted from the external lpf for automatic control. summary of operation when the focus and spindle servos are on, tracking balance control turns off the tracking and servo loops to open the tracking loop, extracts the dc offset by sending the error signal, passed through the optical pick-up and tracking error amp, through the external lpf, then this offset to the previously set window comparator level, and then informs of the completion the balance control to the micom through the istat, when the dc offset of the tracking error amp in window is extracted. at this time, tracking e beam-side i/v amps gain is selected by micom, and the 5-bit resistance arrays resistance value is selected by the 5-bit control signal. the values that micom applies are 00000 ? 11111. if you select the switch, teso dc offset increases the (2.5v- d v) ? (2.5v + d v) one step at a time, to enter the pre-selected dc window level. when it enters that level, the balance adjust is completed, and the switch condition is latched at this time because the teso signal frequency is distributed up to 2khz, the dc offset that passed through the lpf is not a correct value, if a dc component exists, and therefore, micom monitors the window output when the teso signal frequency is above 1khz. at this time, the frequency check the istat pin. when tbal output is h, balance control is complete. vdc < rli rf amp & servo signal processor s1l9226x 5 preliminary ? rhi: high level threshold value ? rli: low level threshold value ? vdc: window comparator input voltage ? tbal: and gate output value of the window comparator output an example of tracking balance control out of $8000 ? $801f 32 steps, the upper and lower 32 steps are used and recommand the clv to clv-p mode. after receiving $8110 as the gain when the focus and tracking are on, the control flow checks trcnt frequency in istat to see if the more than 7 trcnt entered during 10ms. if yes, it checks the istat, if no, it checks the number of trcnt three times and goes on to the istat check. repeats fail, it raises the balance switch by 1 step. if istat does not immediately go to h, it for 10 ms during istat check after which it check whether istat is h continuously for 10ms, is repeated three times. if the three repeats fail, it raises the balance switch by 1 step. the above wait 10 ms while running the system. it finds the average of the values obtained the three repeated execution of the entire above balance control. if only the balance values are from two of the three repeats, these values are averaged. if only two out of the three tries were successful in getting a balance value, average the two values. set as balance switch, this average value +2. this is because the balance for the system and the minus value for the dc is stable in the system. precision is important in balance adjust, and about 1+2 sec is spent as adjust time, which is accounted for. balance control flowchart 1 start - environment setting focus on $08 spindle on clv-p mode tracking off $20 sled off gain $8110 balance window level setting check to see if trcnt is 7 for 10ms istat = h? present control value +2 step then, adj end. b0 to b4 switch control balance adj. start $8000 other method - can balance adjust while moving tracks - $f03 easy to trcnt freq check in the 2x mode -20mv - +20mv $84 x0xx -30mv - +30mv $84 x1xx almost 20mv is istat = h? check if istat is h after waiting 10ms repeat 3 times change switch if failure after 3 repeats repeat 3 times change switch if failure after 3 repeats no yes yes no balance adj. switch incnease by 1 step $8000 -> $801f if finds the average of the values obtained the three repeated execution of the entire above bacance control. if only two out of the three tries ware successtial in getting a bacance value, average the two value.
s1l9226x rf amp & servo signal processor 4 preliminary balance control flowchart 2 when tracking balance ? the balance adjust is from $8000 to $801f, and the switch mode is changed one step at a time by 16-bit data transmission. after adjustment, a separate latch pulse is not necessary. ? if the trcnt freq. is not high enough, the balance control can be adjusted at $f03 applied 2x mode . ? here, we have suggested tracking off status for the balance adjust, but the same amount of flow can be balance adjusted while in track move. ? among the 16 bit data, the tracking balance window setting level can be selected from 0: -20 mv ? +20mv 1: -30mv ? +30mv through the d6 bit. ? when the tracking balance adjust is complete, the tracking gain control starts. start environment setting - focus on $08 - spindle on clv-p mode - tracking off $20 - sled off gain $8110 balance window level seting trcnt freq is high enough? istat = h? end adj. b0 to b4 switch control balance adj. start $8000 other method - can balance adjust while moving tracks - $f03 easy to trcnt freq. check in the 2x mode balance adj. switch incnease by 1 step $8000 -> $801f -20mv - +20mv $84 x0xx -30mv - +30mv $84 x1xx no yes yes 1khz check no
rf amp & servo signal processor s1l9226x 5 preliminary tracking balance equivalent resistance tracking balance fixed resistance and parallel resistance variable resistance (5bit) data tsio offset f equi- valent res. e equi- valent res. 100k/ 5bit r 5bit equi- valence 35k 70k 140k 280k 560k comments $8000 391k 480k 15.22k 17.9k 1 1 1 1 1 $8001 391k 475k 15.6k 18.6k 1 1 1 1 0 $8002 + 391k 468k 16.1k 19.3k 1 1 1 0 1 $8003 391k 463k 16.5k 19.7k 1 1 1 0 0 $8004 391k 455k 17.2k 20.8k 1 1 0 1 1 $8005 391k 451k 17.6k 21.5k 1 1 0 1 0 $8006 391k 444k 18.3k 22.4k 1 1 0 0 1 $8007 391k 439k 18.9k 23.3k 1 1 0 0 0 $8008 391k 433k 19.5k 24.3k 1 0 1 1 1 $8009 391k 426k 20.4k 25.5k 1 0 1 1 0 $800a - 391k 421k 21.0k 26.6k 1 0 1 0 1 70k//35k = 23.3k 1 $800b 391k 415k 21.9k 28.0k 1 0 1 0 0 280k//140k = 93.3k 2 $800c 391k 409k 22.7k 29.4k 1 0 0 1 1 560k//280k = 186.6k 3 $800d 391k 403k 23.7k 31.1k 1 0 0 1 0 140k//35k = 28k 4 $800e 391k 397k 24.7k 32.9k 1 0 0 0 1 280k//35k = 31.1k 5 $800f 391k 391k 25.9k 35k 1 0 0 0 0 560k//35k = 32.9k 6 $8010 391k 385k 27.1k 37.2k 0 1 1 1 1 140k//70k = 46.6k 7 $8011 391k 380k 28.5k 39.9k 0 1 1 1 0 280k//70k = 56k 8 $8012 391k 374k 30.0k 43.0k 0 1 1 0 1 560k//70k = 62.2k 9 $8013 391k 368k 31.7k 46.6k 0 1 1 0 0 1//2 = 18.56k 10 $8014 391k 361k 33.9k 51.4k 0 1 0 1 1 10//560k = 17.96k $8015 391k 357k 35.8k 56k 0 1 0 1 0 $8016 391k 350k 38.3k 62.2k 0 1 0 0 1 $8017 391k 344k 41.1k 70k 0 1 0 0 0 $8018 391k 336k 44.5k 80.4k 0 0 1 1 1 $8019 391k 332k 48.4k 93.9k 0 0 1 1 0 $801a 391k 327k 52.8k 112k 0 0 1 0 1 $801b 391k 321k 58.3k 140k 0 0 1 0 0 $801c 391k 315k 65.1k 187k 0 0 0 1 1 $801d 391k 309k 73.6k 280k 0 0 0 1 0 $801e 391k 303k 84.8k 560k 0 0 0 0 1 $801f 391k 298k 100k 0k 0 0 0 0 0 252k 13k 26k f equivalence resistance 252k 13k 5bit e equivalence resistance
s1l9226x rf amp & servo signal processor 4 preliminary tracking gain control concept operation summary tracking gain control is executed by comparing the previously set gain set value of the window with the only the pure ac component of the signal teio (dc+ac) , which was extracted the resistance divide of the tracking error amp output, passed through the lpf and dc offset . the resistance divide regulates the gain by changing the 5 bit resistance combination with micom command. the tracking gain control is executed under the balance control, the same of focus loop on, spindle servo on, tracking servo off and sled servo off and controls amount of optical pick-up reflection and tracking error amp gain. external lpf cut-off freq. is 1o 10hz - 100hz. the window comparator comparison level can be selected between +150mv - +300mv and +250mv - 200mv using the micom command. tgl outputs the +150mv and +250mv comparator outputs to trcnt. tgh outputs the +300mv and +200mv comparator outputs to istat. gain control completes control when tgl output is h. vac < gli rf amp & servo signal processor s1l9226x 5 preliminary tracking gain control ? in balance control, 16 bit data transmission changes the switch mode by 1step from $811f ? $8100, and , after adjustment, a separate latch pulse is not needed. ? the h duty check reference of tgl output of trcnt output is above 0.1ms. ? the most appropriate method is chosen among the 4 control modes listed besides the ones above for control. ? among the 12 bit data, the tracking balance window setting level can be selected from 0: +250mv (tgl) - +200mv (tgh), 1: +150mv (tgl) - +300mv (tgh) through the d3 bit. ? when the tracking gain adjust is complete, it enters the tracking & sled servo loop and toc read. window input tgh (pin19) tgl (pin18) ghi gli vac 1 2 3
s1l9226x rf amp & servo signal processor 4 preliminary gain control flowchart 1 in gain control, the micom command from $811f ? $8100 successively executes the down command and goes status 1 to 2 ? 3. if it reaches status 2, control ends. ? gain control method 1 the micom monitors the tgl output of istat and, when it detects the output's h duty (0.1ms), ends. the window comparator level at this time is +150mv - +300mv. ? gain control method 2 the micom monitors the tgh output of istat and, when it detects the output's h duty (0.1ms), ends. the window comparator level at this time is +150mv - +300mv. ? gain control method 3 the micom monitors the tgl output of istat and, when it detects the output's h duty (0.1ms), ends. it changes the window comparator level at this time from +150mv - +300mv to +250mv - +200mv. then it re- monitors the tgl output of istat, and, if it detects the output's h duty (0.1ms), control ends. if it latches the middle command between the previous micom command value and latter command value, +200mv gain control becomes possible. ? gain control method 4 the micom monitors the tgl output of istat and, when it detects the output's h duty (0.1ms), it down the micom command by 1 and control ends. the window comparator level at this time is +150mv - +300mv. ? gain control method 5 gain control is set to 32 steps in total and gain window is set to +250mv. (that is, start from $811f and head toward $8110) after setting $811f, it monitors the istat to check whether five istat were detected for 10ms. if yes, control ends, and, if not, it as gain switch is lowered by 1 step. the above process is repeated three times and the average value obtained from this repetition set as the gain control switch. start - environment setting focus on $08 spindle on, clv-p mode tracking off $20 sled off gain window level setting istat = h? end adj. g0 to g4 switch control gain adj. start $83f separate environment setting is not required when controlling the gain after controlling balance +150mv - +300mv $84 1xxx +250mv - +200mv $84 0xxx yes no 32 tep reduction of gain adj. switch from $811f -> $8100
rf amp & servo signal processor s1l9226x 5 preliminary gain control flowchart 2 start - environment setting focus on $08 spindle on, clv-p mode tracking off $20 sled off balance window level setting are there 5 istat for 100ms? end adj. g0 to g4 switch control gain adj. start $811f separate environment setting is not required when controlling the gain after controlling balance +150mv - +300mv $84 1xxx +250mv - +200mv $84 0xxx yes no 32 tep reduction of gain adj. switch from $811f -> $8110 gain switch seting after averaging the 3 repeats
s1l9226x rf amp & servo signal processor 4 preliminary tracking gain equivalent resistance tracking gain data terr gain terr gain 5bit gain ratio proportional resistance combined resistance 7.5k 7.5k 3.75k 2.0k 1k comments $811f 0.096 96k/32k 0.032 15.0k 0.5k 1 1 1 1 1 the gain at $811e 0.272 ? x 3.0 0.090 15.0k 1.5k 1 1 1 1 0 ratio is $811d 0.428 0.142 15.0k 2.5k 1 1 1 0 1 calculated in $811c 0.567 0.189 15.0k 3.5k 1 1 1 0 0 the tsio $811b 0.662 0.220 15.0k 4.25k 1 1 0 1 1 terminal. $811a 0.777 0.259 15.0k 5.25k 1 1 0 1 0 $8119 0.882 0.294 15.0k 6.25k 1 1 0 0 1 $8118 0.977 0.325 15.0k 7.25k 1 1 0 0 0 $8117 1.043 0.347 15.0k 8.0k 1 0 1 1 1 $8116 1.144 0.381 15.0k 9.25k 1 0 1 1 0 $8115 1.200 0.400 15.0k 10.0k 1 0 1 0 1 $8114 1.269 0.423 15.0k 11.0k 1 0 1 0 0 $8113 1.317 0.439 15.0k 11.75k 1 0 0 1 1 $8112 1.378 0.459 15.0k 12.75k 1 0 0 1 0 $8111 1.434 0.478 15.0k 13.75k 1 0 0 0 1 $8110 1.487 0.495 15.0k 14.75k 1 0 0 0 0 $810f 1.548 0.516 7.5k 8.0k 0 1 1 1 1 $810e 1.636 0.545 7.5k 9.0k 0 1 1 1 0 $810d 1.714 0.571 7.5k 10.0k 0 1 1 0 1 $810c 1.783 0.594 7.5k 11.0k 0 1 1 0 0 $810b 1.860 0.620 7.5k 12.25k 0 1 0 1 1 $810a 1.888 0.629 7.5k 12.75k 0 1 0 1 0 $8109 1.941 0.647 7.5k 13.75k 0 1 0 0 1 $8108 1.988 0.662 7.5k 14.75k 0 1 0 0 0 $8107 2.021 0.673 7.5k 15.50k 0 0 1 1 1 $8106 2.0625 0.6875 7.5k 16.50k 0 0 1 1 0 $8105 2.100 0.700 7.5k 17.50k 0 0 1 0 1 $8104 2.134 0.711 7.5k 18.50k 0 0 1 0 0 $8103 2.158 0.719 7.5k 19.25k 0 0 0 1 1 $8102 2.189 0.729 7.5k 20.25k 0 0 0 1 0 $8101 2.217 0.739 7.5k 21.25k 0 0 0 0 1 $8100 2.243 0.747 7.5k 22.25k 0 0 0 0 0
rf amp & servo signal processor s1l9226x 5 preliminary example of systam control power on disc tray check loading focus error febias automatic control start $878 +$87f+$841 transfer replay disc change focus offset cancel automatic control start $08+$867+(200ms wait)+ $86f+$842 transfer tracking offset cancel start $8f1f -> $8f00 (istat->h) laser diode on ld on, p-sub $8560 transmission limit sw check focusing auto-focusing $47 transmission spindle servo loop on tracking & sled loop off $20 transmission tracking balance adjust tracking gain adjust toc read ok? disc 8/12cm check play back 100ms istat l -> h? 100ms istat l -> h? time 100ms maximum 100ms maximum 2s maximum 300ms maximum try count 3? laser off $850 transmission display (no disc) standby laser off $850 transmission display (error), tray open standby fail no yes pass no yes close open focus ok? fok h?
s1l9226x rf amp & servo signal processor 4 preliminary febias offset control febias offset control starts when it receives the febias offset control start command $841x from the micom. febias offset control ends when the focus error amp output above 1/2 vcc after the focus output with 1/2 vcc at the focus error amp final output terminal. the voltage per 1 step of the focus offset control is approximately 17mv. the 5bit resistance dac changes from 112mv up to - 112mv in 1 step, after which 1/2 step, approximately -8mv offset, is applied. the offset dispersion after febias offset control exists between -8mv - +8mv. the time per 1 step is 2.5ms; for 5 bits and total of 32 steps, the maximum required time is 128ms. hardware performs the control from minus offset to plus offset. the febias offset re-control is when 4bit dac is reset by $878. and reset can be canceled only when the $87f applied d2 bit is changed from 0 ? 1. the febias dac latch block reset for electrostatics and system operation is reset by micom data and not by reset terminal, the system reset. x1 x2 x4 x8 3k + - + - 160k 4k 32k 32 + - fcmpo 164k vb va 11 fsi vc
rf amp & servo signal processor s1l9226x 5 preliminary focus offset control focus offset control starts when it receives the focus offset control start command $842x from micom. focus offset control ends when the focus error amp output below 1/2vcc after the focus output with 1/2 vcc at the focus error amp final output terminal. the voltage per 1 step of the focus offset control is approximately 40mv. the 4 bit resistance dac changes from 320mv up to -320mv in 1 step, after which 1/2 step, approximately -20ms offset, is applied. the offset dispersion after focus offset control exists between -20mv - +20mv. the febias offset can be changed in 10mv step within the micom's 100mv range after focus offset control. the required per 1 step is 2.5ms; for 4 bits and total of 16 steps, the maximum required time is 128ms. for focus offset readjust, 4-bit dac is reset by $867, and reset can be canceled only when the $86fx applied d3 bit is changed from 0 ? 1. the febias dac latch block reset for electrostatics and operation error is reset by micom data and not by reset terminal, the system reset. 31 + - focus phase compensation - + ps 4 3 0 0 1 1 0 1 0 1 x1 x2 x3 x4 + - + - + - 30 7 9 10 11 8 3.6k 60k fzc i dfcti 48k fs4b fs3 580k fgd fsi 20k 470k 40k fs2b 82k 40k 10k 50k 5k fs1 fset flb frch fem feo to digital vc
s1l9226x rf amp & servo signal processor 4 preliminary febias offset setting febias control the febias offset control is automatically controlled to 0mv and can be controlled to 200mv. after the focus offset automatic control ends after febias offset automatic control, the command sets the internal positive and negative offsets in 20mv units to the micom. rf summing amplifier appication the rf i/v amp can be controlled to 0.5x 8step up to 1x - 4x cd-r and cdrw. the information related to cdr, cdrw disc detector is output as rfo level through the istat. the rfo offset control is installed to prevent rf level clipping during low rfo voltage. 39 pdac rfm pdbd + - + - rf offset control rfo 1 cdrw gain sel 10k cdrw gain sel iv amp 10k 22k 2pf + - 2 33pf 40
rf amp & servo signal processor s1l9226x 5 preliminary rf equalize & agc the modulator output, which had the veqc's tanh term multiplied at the input, passes through the approximately 3x gain terminal to the arf pad. on the one hand, the output is - rectified as it passes through the hpf having 50khz pole frequency and follows the peak envelope the rf level. at this time, the pole frequency of the hpf is set to 50khz so that the 3t - 11t component can pass through without attenuation. the rf level peak value is integrated at the 's cap node after wave rectification. if this peak value is less than the already set voltage comparison, sinking current is output and, if not, sourcing current is output. the maximum peak value at this time is 10ua, which is i/v converted and applied as the modulator control voltage. under the sinking condition, the vcagc increases to 1outx10k and multiplied by tanh (1-x); the sourcing condition, vcagc decreases to iout x10k and multiplied by tanh (1+x), where x is (veqc/2vt). overall, after detecting the 3t and 11t levels by full-wave rectification, it is compared to tanh using the modulator and multiplied to the gain to realize the wave-form equalize. the above is related to the agc concept, which means that a specific rf level is always taken modulator 3x gain amp hpf (3db: 50khz) i/v converter control range i * 10k full wave rectifier (rf peak envelope) iout = 2gm (vid/2) = gm * vid = (iref) * (vid/vt) = iref * (vp-vn)/vt if vn > vp vcagc increment (tanh (1-x)) if vn < vp vcagc decrement (tanh (1+x)) tanh 0.1 = 0.1 tanh 0.5 = 0.462 tanh 0.1 = 0.7 tanh 2.0 = 0.964 vref vp vn v = i/c (115pf) eqo-agc output vin (t) vcagc (t) vo (t) + - vin(t) = 0.73x (rfo) vo(t) = r6 (5.5k) r5 (7.5k) vin (t) tanh ( 2vt vcagc(t) )
s1l9226x rf amp & servo signal processor 4 preliminary other block tracking error amplifier the side spot photo diode current input to terminals e and f passes through the e loop i-v and f loop i-v amps. it is then converted into voltage, in order to gain the difference signal in the tracking error amp. this portion can perform 0.5x 8 step gain control up to 1x-4x for cd-r and cd-rw. has the micom programming, which controls the balance by controlling gain at the e terminal and controls the gain at teio. focus ok circuit focus ok circuit makes the timing window, which turns on the focus in the focus search state by "output" fok as l ? h if the rf level is above the reference after the difference in dc between and rfo terminals extracted and compared to the reference dc value. 13 42 41 34 pde pdf teio + - cd-rw, cd gain sel cd-rw, cd gain sel 35 lpft win comp win comp b_ref_cn g_ref_cntr gain_up/d gain < 4: bal < 4:0 > 16r 8r 2r 4r r 3 2 eqi rfo + - + - 40k 40k 40k 57k 90k vc + 0.625v fokb
rf amp & servo signal processor s1l9226x 5 preliminary mirror circuit after amplifying the rfi signal, the mirror signal peak and bottom holds. peak hold can follow even at defect type traverse and bottom hold counts the tracks by following rf envelop at a jump. the mirror output is "l" on the disc track and "h" between tracks. even if above 1.4 ms is detected, it outputs "h". efm comparator the efm comparator makes the rf signal into a secondary signal. the asymmetry generated by a fault during disc production cannot be eliminated by only ac coupling, so control the standard voltage of the efm comparator to eliminate it. 3 eqi + - 17k 19k 38k peak and bottom hold + - + - + - 44 mcp mirror 80k 96k 17k 1.5k 5 + - 40k efmi - rf double asymmetry conection - efmi peak prevention system - asymmetry hold system 22 asy 21 efm x5
s1l9226x rf amp & servo signal processor 4 preliminary defect circuit after rfo signal inversion, bottom hold is carried out using only 2. except, the bottom hold of holds the coupling level just before the coupling. differentiate this with the coupling, then level shift it. compare the signals to either direction to generate the defect detect signal. apc circuit when the laser diode operates in electrostatic field, the laser output temperature highly negative so the monitor photo diode controls the laser output at a fixed level. the laser control system is installed to absorb the deviation of the disc reflection. system controls the laser power using the tracking summing signal of the side beam to a fixed laser output. 2 rfo + - 37.5k 75k 75k bottom envelope + - 45 dcc1 defect bottom envelope 43 dcb 46 dcc0 28k vc vc+0.6254v 43k 38 pd 37 ld + - + - laser control ldon 5k 5k 55k 0.25k 55k 5k 55k
rf amp & servo signal processor s1l9226x 5 preliminary center voltage generation circuit the center voltage is made by using the resistance divide. rf equalize circuit the agc block, which maintains the rf peak to peak level, possess the 3t gain boost. it detects the rf envelop and compares it to the reference voltage to control the gain. receives the rf output to stabilize the rf level to 1vpeak-peak, which is applied to the efm slice input. atsc the detection circuit for shock tracking gain up is composed of the window comparator. + - 30k vref 47 30k 3 eqi 48 eqc equalize vca 4 eqo 36 atsc bpf + - + - tracking gain up
s1l9226x rf amp & servo signal processor 4 preliminary focus servo if the focus servo loop phase has been compensated, the focus servo loop mutts if the defect is. the focus error signal at this time is differentiated by the 0.1uf capacitor to be connected to the terminal and the 470kohms resistance and is output es through the servo loop. therefore, the focus output is held to value before the defect error during defect. the fset terminal changes the at which the focus loop compensation is at its maximum. if the resistance to vdda connected to the terminal, the phase compensation frequency is changed 1.2khz below, and gnd connected to the terminal, the frequency is changed 1.2khz above. during focus search, fs4 turns on to cutoff the error signal and to output the focus search signal through the feo. when the focus is on, fs2 turns on, and the focus error signal input through the fsi is output through the loop to the output pin. 31 + - focus phase compensation - + ps 4 3 0 0 1 1 0 1 0 1 x1 x2 x3 x4 + - + - + - 30 7 9 10 11 18 3.6k 60k fzc i dfcti 48k fs4b fs3 580k fgd fsi 20k 470k 40k fs2b 82k 40k 10k 50k 5k fs1 fset flb frch fem feo to digital vc
rf amp & servo signal processor s1l9226x 5 preliminary tracking servo the tracking servo phase compensate the tracking servo loop and differentiates the tracking error signal, after which it outputs the signal through the servo loop. tgu exchanges the tracking gain up/down time constant. as in the focus loop, the phase compensation peak frequency is varied by the fset terminal. if the resistance connected to the fset terminal changes, the op amp dynamic range offeset changes also. the tm7 switch is a brake switch which turns the tracking loop on/off when the actuator is unstable after a jump. after the servo jumps 10 tracks, the servo circuit leaves the linear range and the actuator sometimes pursues the unstable track, preventing unnecessary jumps from undesired tracking errors. as the terminal which controls the tracking servo loop's high frequency gain, the tgu terminal controls the desired frequency range of the gain through the external cap. 29 8 34 teio fset 90k teo tracking phase compensation 12 tgu tlpfi dfcti 680k + - 28 tem 10k tm7 68p f 680k tg1b 10k 110k 82k tm1 470k tg2b tm4 tm3
s1l9226x rf amp & servo signal processor 4 preliminary sled servo this servo differentiates the tracking servo and moves the pick-up. it also outputs the sled kick voltage to make a track jump in the sled axis during track movement. spindle servo & low pass filter the 200hz lpf, composed of an external 20kohms resistance and 0.33uf cap, eliminiates the high frequency carrier component. 27 + - 25 slm tm6 tm7 26 slo tm2 ps 2 1 0 0 1 1 0 1 0 1 x1 x2 x3 x4 slp + - 23 spm 24 sp0 100k + - 8 fset 18 clvi 50k fvco double speed 30k 30k 220k 220k
rf amp & servo signal processor s1l9226x 5 preliminary mirror & cpeak mute (use only for tracking mute ) used against abex-725a, this circuit processes the tracking mutting when mirror is detected. (no recommend) the tracking mutting when efm duty is above 22t after it is checked. mute does not operate in the following four cases. ? micom tracking gain up command transmission (tg1, tg2 = 1) ? anti-shock detection (atsc) ? lock falls to l ? defect detection trcnt output trcnt is output of mirror and tzc. mirror is the track movement detection output of the main beam; tzc is the track movement detection output of the side beam. trcnt receives these two inputs to determine whether the present pick-up is moving from the inside to the outside or from the outside to the inside. it is used at $17 tracking brake operation. mirror tzc inverter delay tzc edge detection. d q ck trcnt output tzc rising, falling edge mirror output.
s1l9226x rf amp & servo signal processor 4 preliminary notes

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